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Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major.
- Step 1 of 6
To compute the effective CPI of IMPS, the CPI formula will beapplied after performing the following operations:
• First calculate the average instruction frequencies of the gapand gcc.
• Divide the major instructions in four categories. Thesecategories also contain two subcategories for conditionalbranches.
Here, round to even scheme is applied to find the averageof gap and gcc. It is because the sum of gap is 100.2 and the sumof gcc is 99.5. It is due to rounding error, because each totalmust consists 100. Therefore, to remove this error the schemeround to even be applied. In this scheme, the leastsignificant digit will always be made even.
- Step 2 of 6
The four main categories are given below:
ALU: In this the operands are taken from the set ofregisters and also that set of registers are returned asresult.
The instructions add, mul, compare, sub, load imm, cond move,shift, or, xor, and, other logical are categorized under ALUinstruction’s frequency.
The following table shows the average instruction frequencies ofgap and gcc for ALU instruction’s category.
Instruction
Average of gap and gcc percentage
XOR
2.0
shift
2.4
mul
0.8
OR
8.2
load imm
3.6
cond move
0.5
and
4.4
sub
2.0
compare
4.4
add
20.0
other logical
0.2
• The ALU instruction’s frequency will be calculated by addingthe frequencies of add, mul, compare, sub, load imm, cond move,shift, or, xor, and, other logical.
• Hence, the total ALU instruction’s frequency will be.
- Step 3 of 6
Load/store: It is used to access memories.
The instructions load and store are categorized under load/storeinstruction’s frequency.
The following table shows the average instruction frequencies ofgap and gcc for load/store instructions.
Instruction
Average of gap and gcc percentage
store
11.8
load
25.8
• The load/store instruction’s frequency will be calculated byadding the frequencies of load and store.
• Hence, the total load/store instruction’s frequency willbe.
- Step 4 of 6
Conditional branches: Depending upon the differentcondition, a new value is given to the program counter.
The following table shows the average instruction frequencies ofgap and gcc for load/store instructions.
Instruction
Average of gap and gcc percentage
cond branch
10.7
• The conditional branches instruction’s frequency will becalculated by taking the frequencies of load cond branch
• The conditional instruction’s frequency will be
- Step 5 of 6
Jumps: A new value is set to the program counter nomatter what.
The following table shows the average instruction frequencies ofgap and gcc for jump instructions.
Instruction
Average of gap and gcc percentage
return
1.1
call
1.1
jump
0.8
• The jump instruction’s frequency will be calculated by addingthe instructions jump, return and call.
• Hence, the total jump instruction’s frequency will be.
Hence, the effective CPI will be calculated as:
- Step 6 of 6
Hence, the effective CPI for MIPS using figure A.27 is.
- ALU instruction frequency = 45.8% or 0.458 also, the load/store instruction frequency = is 37.6% or 0.376 which was not shown correctly during the calculations (0.367 x 1.4) another typo, other than that I really appreciate the work.
Winner of a 2019 Textbook Excellence Award (Texty) from the Textbook and Academic Authors AssociationIncludes a new chapter on domain-specific architectures, explaining how they are the only path forward for improved performance and energy efficiency given the end of Moore’s Law and Dennard scalingFeatures the first publication of several DSAs from industry Features extensive updates to the chapter on warehouse-scale computing, with the first public information on the newest Google WSC Offers updates to other chapters including new material dealing with the use of stacked DRAM; data on the performance of new NVIDIA Pascal GPU vs. new AVX-512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organizationIncludes 'Putting It All Together' sections near the end of every chapter, providing real-world technology examples that demonstrate the principles covered in each chapter Includes review appendices in the printed text and additional reference appendices available online Includes updated and improved case studies and exercisesACM named John L. Hennessy and David A. Patterson, recipients of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry